1. Field of the Invention
The present invention relates to an information processing device such as a microprocessor, a DSP (Digital Signal Processor) or the like, and more particularly, to a control technique of instruction fetch with an information processing device.
2. Description of Related Art
An information processing device generally includes an instruction fetch unit that fetches an instruction from an instruction memory (instruction cache or ROM, for example), and an instruction executing unit that decodes the instruction that is fetched for execution. Further, in order to smoothly supply the instruction to the instruction executing unit, an instruction buffer is normally disposed between the instruction fetch unit and the instruction executing unit. In the information processing device having such a structure, the instruction fetch unit sequentially fetches the instructions independently from a pipeline processing after the instruction decoding in the instruction executing unit, and the instructions obtained from the instruction memory are stored in the instruction buffer. This precedent instruction fetch operation that is performed independently from processes after the instruction decoding is called instruction prefetch.
More specifically, the instruction fetch unit includes a fetch pointer which is a register to store an address of a fetch target instruction, and supplies a value of the fetch pointer to the instruction memory. The instruction fetch unit performs instruction fetch while sequentially updating the value of the fetch pointer in accordance with a data reading unit from the instruction memory. The data reading unit from the instruction memory can be rephrased as “a bus width between the instruction memory and the information processing device”. Further, the instruction fetch unit includes a mechanism to discontinuously change the value of the fetch pointer to a branch destination address due to the occurrence of interruption, exception, decoding of a branch instruction or the like.